It is often necessary to generate a supply voltage internally within an integrated circuit. Memory circuits, for example, may require the internal generation of a specialized supply voltage as a boosted wordline supply voltage (for example at 3.3V) or as a negative wordline low supply (for example at -0.5V). A charge pump is a device readily incorporated onto an integrated circuit which can be used to generate and maintain an internal supply voltage from an external voltage supply.
By way of illustration only and not intended to limit the meaning of "charge pump" to that particularly shown, FIG. 9 shows a simple schematic for a charge pump 250 used to generate a supply voltage Vout from a first constant voltage input Vdd. The charge pump 250 receives a CLK input, which determines the charge transfer rate, and a control signal P1, which controls on-off switching of the charge pump. As will be understood, CLK provides the charge pump clock signal Vclk and its inverse /Vclk at which capacitors CP2 and CP1 are alternately held. During a first half cycle of CLK, Vclk is held high, /Vclk is held low and CP1 is charged from the voltage input Vdd such that the voltage on CP1 rises toward /Vclk+Vdd. During a second half cycle of CLK, Vclk falls low, while /Vclk is raised high. This causes the potential on CP1 to rise, while the potential on CP2 temporarily falls such that charge stored on CP1 is transferred to CP2. Finally, during a second full cycle of CLK, charge is transferred from CP2 onto the generated voltage supply output Vout.
Demand for current from a supply voltage varies depending on the operational state of the integrated circuit. For example, in many systems such as computers and printers, a memory chip is sometimes operated in an active mode in which relatively high current is required; for example, to access data on the chip, and at other times is operated in a standby mode or "sleep mode" in which relatively little current is required, such as is required to merely protect internal steady state voltage levels, e.g. Vbleq against leakage currents when no memory cells are accessed.
FIG. 10 shows an example of a prior art charge pump system having both active charge pumps 124 and a standby charge pump 126. The active pumps 124 are enabled by a "pump enable" signal P1, while the standby charge pump 126 remains continuously enabled to supply current to the chip, such as is required to maintain the voltage level of the supply Vout against degradation from charge leakage. The active pumps 124 are designed to meet the large demands for current of active operation and therefore, have a higher pumping rate, i.e. have higher capacity or higher charge transfer rate, than the standby charge pump 126. On the other hand, the standby charge pump 126 is designed to consume little power and to maintain the output voltage at a nearly constant level for long periods of time and thus is designed with a lower pumping rate, i.e. is slower.
The standby pump 126 is only needed to replenish the charge that leaks away during standby mode or sleep mode, when no wordlines are activated within the chip. At any time that a wordline is activated for access to a stored bit or for a refresh operation, the active pumps are switched on. The standby charge pump 126 operates continuously at a single and slower speed compared to the active pump; i.e., based on a CLK frequency that does not change. Heretofore, because the standby charge pump was continuously operated at lower output current than active charge pumps, the standby pump had to be designed as a separate unit dedicated to that function. However, although the standby charge pump 126 provides considerably less output current than an active charge pump 124, the chip area required to implement the standby charge pump 126 is comparable to that required to implement the active charge pump 124.
FIG. 11 is a timing diagram illustrating the operation of the prior art charge pump system shown in FIG. 10. Active charge pumps 124 are conventionally driven by a ring oscillator that has a fixed output frequency which functions as a CLK input to the charge pump in a similar manner to the charge pump described above with reference to FIG. 9. Consequently, in an "active interval" of operation, active charge pumps 124 cause the output voltage to rise and fall relatively quickly, because the active charge pumps 124 can only be activated or deactivated based on the output voltage Vout exceeding a single reference voltage Vref. The level of "ringing" depends on the limiter speed and the impedance of the wiring. A limiter with a slower feedback speed and high wiring resistance results in higher level of ringing. This is because when the limiter detects the output level below the target level, it will activate a control signal (not shown) to turn the pump on. First, it takes time to trigger the control signal, then it takes more time to communicate the control signal along the wiring back to the charge pump. During these times, the voltage level will continue to undershoot. Similarly, when the limiter detects the output level has reached the target level, it generates a control signal to shut off the charge pump. However, the delay in generating the control signal and communicating it back to the charge pump causes the voltage level to overshoot.
One way to reduce such ringing would be to utilize a high speed limiter. However, high speed limiters are generally considered unsuitable because of their high power consumption owing to the use of a resistive voltage divider and a differential amplifier which draw high DC current. Another possibility would be to decrease wiring impedance by using wider conductors. However, doing so would directly contribute to an increase in chip area. The relatively large "ringing" in the Vout voltage level introduces noise into the memory chip. The standby charge pump 126 also operates during the active interval, but its output current has little effect upon the rise and fall of Vout, its output current being much smaller than that of the active charge pumps 124.
In a standby interval of operation, the active pumps 124 are switched off by the pump enable signal P1 becoming disabled. However, the standby pump 126 is not disabled, but continues to operate when needed to restore the output voltage Vout to its target level. In this manner the output voltage Vout is maintained at or near its target level during both active and standby intervals.
It is an object of the present invention to provide a charge pump system in which the dedicated standby charge pump is eliminated, thereby reducing the layout area on the semiconductor chip.
It is another object of the invention to provide a charge pump system in which the rate of charge transfer to the voltage supply varies as a function of the voltage level reached by the voltage supply.
Still another object of the invention is to provide a charge pump system in which different groups of charge pumps are independently switched on and off in response to the voltage supply reaching different predetermined voltage levels.
Still another object of the invention is to more precisely control the voltage supply level by varying the rate of charge transfer thereto based on the voltage level reached, thereby reducing the amount of ringing and noise coupled onto the voltage supply line.